MC68LC302 Datasheet, PDF (44/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

System Integration Block (SIB)
At this time other desired initialization should be completed on the MC68LC302. No bus
masters (IDMA, SDMA, or external) should be enabled.
While in 8-bit mode, the MC68LC302 should initialize the external memory registers that
control the16-bit external memory space. External memory refresh is not enabled at this
time, but all other desired external memory control features should be enabled. Note that
the MC68LC302 does not access the external memory itself yet, only the external memory
control registers.
The 302-based device now copies a special boot code to the user area of the internal dual-
port RAM of the 302, and then jumps to the start of that code. This code is copied as “data”
to the dual-port RAM.
To summarize, the procedure is then:
• Boot up 302-derivative
• Perform required 8 bit operations
• Write code to the dual port RAM for the bus width change
• Jump to code in the dual port RAM
• When ready to use 16-bit bus width, set the BUSW bit to 1
• Toggle the BWSEN bit from zero to one.
• Allow time for bus arbitration and the instruction pipeline to clear
• Initialize external memory
• Copy boot code from EPROM to external memory space
• Execute code from external memory space
NOTE
The stack which is shared by both codes should be placed in the
dual ported RAM. Copy the stack to dual port RAM after switch-
ing to the second RAM and change the stack pointer.
3.3 LOAD BOOT CODE FROM AN SCC
The MC68LC302 provides the capability of downloading program code into SCC1 and
beginning program execution in the dual port RAM. The boot function has two clocking
options: external and internal.
In the first mode, the user provides the chip with an external clock 16* the desired baud rate.
In the second mode, the RISC processor programs the SCC into UART mode running at
approximately 9600 baud (assuming the frequency of the clock to the chip has one of two
nominal values 32.768 Khz or 4.192 Mhz).
The first 576 bytes that are received into SCC1 are stored in the dual-port RAM. No error
checking is performed on the incoming serial bit stream. The 68000 processor then begins
MOTOROLA
MC68LC302 REFERENCE MANUAL
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