MC68LC302 Datasheet, PDF (115/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
Each of these four pins can be used either as a dedicated timer function or as a general-
purpose port B I/O port pin. Note that the timers do not require the use of external pins. The
input buffers have Schmitt triggers.
TIN1/PB3—Timer 1 Input
This input is used as a timer clock source for timer 1 or as a trigger for the timer 1 capture
register. TIN1 may also be used as the external clock source for any SCC baud rate gen-
erators.
TIN2/PB5—Timer 2 Input
This input can be used as a timer clock source for timer 2 or as a trigger for the timer 2
capture register.
TOUT2/PB6—Timer 2 Output
This output is used as an active-low pulse timeout or as an event overflow output (toggle)
from timer 2.
WDOG/PB7—Watchdog Output
This active-low, open-drain output indicates expiration of the watchdog timer. WDOG is
asserted for a period of 16 clock (CLKO) cycles and may be externally connected to the
RESET and HALT pins to reset the MC68LC302. The WDOG pin function is enabled after
a total system reset. It may be reassigned as the PB7 I/O pin in the PBCNT register.
5.17 PARALLEL I/O PINS WITH INTERRUPT CAPABILITY
The four parallel I/O pins with interrupt are shown in Figure 5-13.
PB8
PB9
PB10
PB11
Figure 5-13. Port B Parallel I/O Pins with Interrupt
PB11–PB8—Port B Parallel I/O pins
These four pins may be configured as a general-purpose parallel I/O ports with interrupt ca-
pability. Each of the pins can be configured either as an input or an output. When configured
as an input, each pin can generate a separate, maskable interrupt on a high-to-low transi-
tion. PB8 may also be used to request a refresh cycle from the DRAM refresh controller rath-
er than as an I/O pin. The input buffers have Schmitt triggers.
5-20
MC68LC302 REFERENCE MANUAL
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