MC68LC302 Datasheet, PDF (101/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
RESET
HALT
BUSW
DISCPU
FRZ
* This pin is available in PGA Package only
Figure 5-3. System Control Pins
RESET
This bidirectional, open-drain signal, acting as an input and asserted along with the HALT
pin, starts an initialization sequence called a total system reset that resets the entire
MC68LC302. RESET and HALT should remain asserted for at least 100 ms at power-on
reset, and at least 10 clocks otherwise. The on-chip system RAM is not initialized during
reset except for several locations initialized by the CP.
NOTE
With a 32.768Khz external crystal the minimum RESET length
is 2.3 seconds
An internally generated reset, from the M68000 RESET instruction, causes the RESET
line to become an output for 124 clocks. In this case, the M68000 core is not reset; how-
ever, the communication processor is fully reset, and the system integration block is al-
most fully rese. The user may also use the RESET output signal in this case to reset all
external devices.
During a total system reset, the address, data, and bus control pins are all three-stated,
except for CS3–CS0, WEH, WEL, and OE, which are high, and IAC, which is low. The BG
pin output is the same as that on the BR input. The general-purpose I/O pins are config-
ured as inputs, except for WDOG, which is an open-drain output. The NMSI1 pins are all
inputs, except for RTS1 and TXD1, which output a high value. CLKO is active.
Besides the total system reset and the RESET instruction, some of the MC68LC302 pe-
ripherals have reset bits in one of their registers that cause that particular peripheral to be
reset to the same state as a total system reset or the RESET instruction. Reset bits may
be found in the CP (in the CR), the IDMA (in the CMR), timer 1 (in the TMR1), and timer
2 (in the TMR2).
HALT—Halt
When this bidirectional, open-drain signal is driven by an external device, it will cause the
LC302 bus master (M68000 core, SDMA, or IDMA) to stop at the completion of the current
bus cycle. This signal is asserted with the RESET signal to cause a total MC68LC302 sys-
tem reset. This signal is also used to force the LC302 off the bus if another bus master
5-6
MC68LC302 REFERENCE MANUAL
MOTOROLA