MC68LC302 Datasheet, PDF (104/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
5.7 BUS CONTROL PINS
The bus control pins are shown in Figure 5-6. The signals shown in parentheses are only
available in DISCPU mode.
AS
OE (R/W)
WEH/A0 (UDS/A0)
WEL/WE (LDS/DS)
DTACK
IAC*
* This pin is available in PGA Package only
Figure 5-6. Bus Control Pins
AS—Address Strobe
This bidirectional signal indicates that there is a valid address on the address bus. This
line is an output when the LC302 (M68000 core, SDMA or IDMA) is the bus master and
is an input otherwise.
OE (R/W)— Output Enable (Read/Write)
When the core is enabled, this output is active during a read cycle and indicates that an
external device should place valid data on the bus.
When the LC302 is in Disable CPU mode, this bidirectional signal defines the data bus
transfer as a read or write cycle. It is an output when the LC302 is the bus master and is
an input otherwise.
WEH (UDS/A0)—Write Enable High (Upper Data Strobe/Address 0)
When the core is enabled with a 16-bit data bus, this output pin functions as WEH and is
active during a write cycle to indicate that an external device should expect data on the
D15-D8 of the data bus.
When the core is enabled with a 8-bit data bus, this bidirectional pin functions as A0.
When the LC302 is in Disable CPU mode, this bidirectional line functions as UDS and
controls the flow of data on the data bus. When using a 16-bit data bus, this pin functions
as an upper data strobe (UDS). When using an 8-bit data bus, this pin functions as A0.
When used as A0 (i.e., the BUSW pin is low), then the pin takes on the timing of the other
address pins, as opposed to the strobe timing. This line is an output when the LC302 is
the bus master and is an input otherwise.
MOTOROLA
MC68LC302 REFERENCE MANUAL
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