MC68LC302 Datasheet, PDF (93/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
4.4.2 SCP Transmit/Receive Buffer Descriptor
The transmit/receive BD contains the data to be transmitted (written by the M68000 core)
and the received data (written by the SCP). The done (D) bit indicates that the received data
is valid and is cleared by the SCP.
15
14
D
RESERVED
8
7
0
DATA
4.5 SERIAL MANAGEMENT CONTROLLERS (SMCS)
The functionality of the SMCs has not changed. For any additional information on parame-
ters, registers, and functionality, please refer to the MC68302 Users’ Manual.
4.5.1 SMC Programming Model
The operating mode of both SMC ports is defined by SMC mode, which consists of the lower
eight bits of SPMODE. As previously mentioned, the upper eight bits program the SCP.
7
6
5
4
3
2
1
0
— SMD3 SMD2 SMD1 SMD0 LOOP EN2 EN1
4.5.2 SMC Memory Structure and Buffers Descriptors
The CP uses several memory structures and memory-mapped registers to communicate
with the M68000 core. All the structures detailed in the following paragraphs reside in the
dual-port RAM of the IMP. The SMC buffer descriptors allow the user to define one data byte
at a time for each transmit channel and receive one data byte at a time for each receive
channel.
4.5.2.1 SMC1 RECEIVE BUFFER DESCRIPTOR. The CP reports information about the
received byte using this (BD).
15
14
13
12
11
10
9
8
7
0
E
L
ER
MS
—
AB
EB
DATA
4.5.2.2 SMC1 TRANSMIT BUFFER DESCRIPTOR. The CP reports information about this
transmit byte through the BD.
4-26
MC68LC302 REFERENCE MANUAL
MOTOROLA