MC68LC302 Datasheet, PDF (73/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Communications Processor (CP)
clocks are present. To restart reception, the ENTER HUNT MODE command should be
issued before ENR is set again.
ENT—Enable Transmitter
When ENT is set, the transmitter is enabled; when ENT is cleared, the transmitter is dis-
abled. If ENT is cleared, the transmitter will abort any data transmission, clear the transmit
data FIFO and shift register, and force the TXD line high (idle). Data already in the trans-
mit shift register will not be transmitted. ENT may be set or cleared regardless of whether
serial clocks are present.
MODE1–MODE0—Channel Mode
00 = HDLC
01 = Asynchronous (UART)
10 = Reserved
11 = BISYNC, Promiscuous Transparent, and Autobaud
4.3.4 SCC Data Synchronization Register (DSR)
Each DSR is a 16-bit, memory-mapped, read-write register. DSR specifies the pattern used
in the frame synchronization procedure of the SCC in the synchronous protocols. In the
UART protocol it is used to configure fractional stop bit transmission. After reset, the DSR
defaults to $7E7E (two FLAGs); thus, no additional programming is necessary for the HDLC
protocol. For BISYNC the contents of the DSR should be written before the channel is
enabled.
15
8
7
0
SYN2
SYN1
4.3.5 Buffer Descriptors Table
Data associated with each SCC channel is stored in buffers. Each buffer is referenced by a
buffer descriptor (BD). BDs are located in each channel's BD table (located in dual-port
RAM). There are two such tables for each SCC channel: one is used for data received from
the serial line; the other is used to transmit data.The format of the BDs is the same for each
SCC mode of operation (HDLC, UART, BISYNC, and transparent) and for both transmit or
receive. Only the first field (containing status and control bits) differs for each protocol. The
BD format is shown in Figure 4-1.
15
0
OFFSET + 0
STATUS AND CONTROL
OFFSET + 2
DATA LENGTH
OFFSET + 4
HIGH-ORDER DATA BUFFER POINTER (only lower 8 bits use, upper 8 bits must be 0)
OFFSET + 6
LOW-ORDER DATA BUFFER POINTER
Figure 4-1. SCC Buffer Descriptor Format
NOTE
Even though the address bus is only 20 bits, the full 32-bit point-
er must be Bits 24-32 must be zero, and bits 20-23 are used in
4-6
MC68LC302 REFERENCE MANUAL
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