MC68LC302 Datasheet, PDF (130/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.9 AC ELECTRICAL SPECIFICATIONS—DMA (see Figure 6-5 and Figure 6-6)
Num.
Characteristic
16.67 MHz 20 MHz
25 MHz
Symbol _{Min Max Min Max Min Max} Unit
83 Clock High to BR Low (see Notes 3 and 4) t_CHBRL — 30 — 25 — 20 ns
84
Clock High to BR High Impedance (see
Notes 3 and 4)
t_CHBRZ — 30 — 25 — 20 ns
85
BGACK Low to BR High Impedance (see
Notes 3 and 4)
t_BKLBRZ 30
—
25
—
20
—
ns
86 Clock High to BGACK Low
t_CHBKL — 30 — 25 — 20 ns
87
AS and BGACK High (the Latest One) to
BGACK Low (when BG Is Asserted)
t_ABHBKL
1.5
2.5
+30
1.5
2.5
+25
1.5
2.5 clks
+20 ns
88
BG Low to BGACK Low (No Other Bus
Master) (see Notes 3 and 4)
t_BGLBKL
1.5
2.5
+30
1.5
2.5
+25
1.5
2.5 clks
+20 ns
89
BR High Impedance to BG High (see Notes
3 and 4)
t_BRHBGH
0
—
0
—
0
— ns
90
Clock on which BGACK Low to Clock on
which AS Low
t_CLBKLAL 2
2
2
2
2
2 clks
91 Clock High to BGACK High
t_CHBKH — 30 — 25 — 20 ns
92 Clock Low to BGACK High Impedance
t_CLBKZ — 15 — 15 — 10 ns
NOTES:
1. BR will not be asserted while AS, HALT, or BERR is asserted.
2. Specifications are for DISABLE CPU mode only.
3. DMA and SDMA read and write cycle timing is the same as that for the M68000 core.
MOTOROLA
MC68LC302 REFERENCE MANUAL
6-13