MC68LC302 Datasheet, PDF (165/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Index
2-15
Low Power Modes
IMP 2-13
Low Power Support 2-15
FAST WAKE-UP 2-18
STOP/ DOZE/ STAND_BY Mode 2-16
Wake-Up from Low Power STOP Modes
2-17
Low-Power Clock Divider 2-9
LPDCR 2-15
LPM1–0 2-15
M
MC68000/MC68008 Modes 2-1
MC68LC302 System Clock Generation
IOMCR 2-6
IPLCR 2-6
IWUCR 2-6
MODCLK 2-7
PITR 2-6
VCCSYN 2-7
MF 11–0 2-11
MODCLK 2-12
MODCLK/PA12 5-5
MODCLK1–0 2-7
Multiplication Factor 2-11
N
NMSI 4-2, 5-14
CD1 5-16
CTS1 5-17
NMSI1 5-15
NMSI2 5-17
NMSI3 5-18
RTS1 5-17
SIMODE 4-2
NMSI1 or ISDN Interface Pins 5-14
NMSI2 Port or Port a Pins 5-17
Normal Operation 4-5
O
OE (R/W) 5-9
OR3–OR0 3-26
Oscillator 2-8
P
PACNT 3-19
PADDR 3-19
PAIO / SCP Pins 5-18
Parallel 5-20
Parallel I/O Pins with Interrupt Capability 5-
20
Parallel I/O Port
PB11 3-18
PB8 3-18, 3-29
Port A 3-17, 5-17, 5-18
Control Register 3-17
Data Direction Register (PADDR) 3-
17
Port B 3-17, 5-20
Control Register 3-18
Parallel I/O Ports 3-17
Parameter RAM 2-21
PB11 3-18
PB11 See DRAM Refresh
PB11 See Parallel I/O Port
PB8 3-18, 3-29
PBCNT 3-18, 3-19
PBDAT 3-20
PBDDR 3-18, 3-20
PCM 4-2
PCM Highway 5-14, 5-15
SIMODE 4-2
Periodic Timer Period Calculation 3-23
Physical Layer Serial Interface Pins 5-14
Pin Assignments 7-1
Pin Grid Array 7-1
PIT 2-11, 2-12, 3-22
As a Real-Time Clock 3-24
Period Calculation 3-23
PIT Clock 2-12
PITR 3-24
PLL 2-10
PLL and Oscillator Changes to IMP 2-5
CLKO Drive Options 2-6
Three-State RCLK1 2-6
Three-State TCLK1 2-6
PLL Clock Divider 2-10
PLL External Components 2-9
PLL Pins
pgnd 5-5
pinit 2-7
INDEX-4
MC68LC302 REFERENCE MANUAL
MOTOROLA