MC68LC302 Datasheet, PDF (111/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
RCLK1/L1CLK—Receive Clock/Layer-1 Clock
This pin is used as an NMSI1 bidirectional receive clock in NMSI mode or as an input clock
in IDL, GCI, and PCM modes. In NMSI mode, this signal is an input when SCC1 is working
with an external clock and is an output when SCC1 is working with its baud rate generator.
TCLK1/L1SY0/SDS1—Transmit Clock/PCM Sync/Serial Data Strobe 1
This pin is used as an NMSI1 bidirectional transmit clock in NMSI mode, as a sync signal
in PCM mode, or as the SDS1 output in IDL/GCI modes. In NMSI mode, this signal is an
input when SCC1 is working with an external clock and is an output when SCC1 is working
with its baud rate generator.
NOTE
When using SCC1 in the NMSI mode with the internal baud rate
generator operating, the TCLK1 and RCLK1 pins will always out-
put the baud rate generator clock unless disabled in the CKCR
register. Thus, if a dynamic selection between an internal and
external clock source is required in an application, the clock pins
should be disabled first in the CKCR register before switching
the TCLK1 and RCLK1 lines. On SCC2, contention may be
avoided by disabling the clock line outputs in the PACNT regis-
ter.
In PCM mode, L1SY1–L1SY0 are encoded signals used to create channels that can be in-
dependently routed to the SCCs.
L1SY1
0
0
1
1
Table 5-9. PCM Mode Signals
L1SY0
0
1
0
1
Data (L1RXD, L1TXD) is Routed to SCC
L1TXD is Three-Stated, L1RXD is Ignored
CH-1
CH-2
CH-3
NOTE: CH-1, 2, and 3 are connected to the SCCs as determined in the
SIMODE register.
In IDL/GCI modes, the SDS2–SDS1 outputs may be used to route the B1 and/or B2 chan-
nels to devices that do not support the IDL or GCI buses. This is configured in the serial in-
terface mode (SIMODE) and serial interface mask (SIMASK) registers.
CD1/L1SY1—Carrier Detect/Layer-1 Sync
This input is used as the NMSI1 carrier detect (CD) pin in NMSI mode, as a PCM sync
signal in PCM mode, and as an L1SYNC signal in IDL/GCI modes.
If the CD1 pin has changed for more than one receive clock cycle, the LC302 asserts the
appropriate bit in the SCC1 event register. If the SCC1 channel is programmed not to sup-
port CD1 automatically (in the SCC1 mode register), then this pin may be used as an ex-
ternal interrupt source. The current value of CD1 may be read in the SCCS1 register. See
5-16
MC68LC302 REFERENCE MANUAL
MOTOROLA