MC68LC302 Datasheet, PDF (106/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Signal Description
BG—Bus Grant
This signal is an input to the IDMA and SDMA when the internal M68000 core is disabled
and indicates that the LC302 has the bus after the current bus cycle completes.
BGACK—Bus Grant Acknowledge
This bidirectional signal indicates that some device has become the bus master. This sig-
nal is an input when an external device owns the bus. This signal is an output when the
IDMA or SDMA has become the master of the bus. If the SDMA steals a cycle from the
IDMA, the BGACK pin will remain asserted continuously.
NOTE
BGACK should always be used in the external bus arbitration
process.
5.9 INTERRUPT CONTROL PINS
The interrupt control pins are shown in Figure 5-8. The IPL2-0 signals are only available
when the CPU is enabled. The FC2-0 and AVEC signals are only available in the PGA
package.
IPL0/IRQ1
IPL1/IRQ6
IPL2/IRQ7
FC0*
FC1*
FC2*
AVEC*
* Those pins are available in PGA Package only
Figure 5-8. Interrupt Control Pins
These inputs have dual functionality:
• IPL0/IRQ1
• IPL1/IRQ6
• IPL2/IRQ7—Interrupt Priority Level 2–0/Interrupt Request 1,6,7
As IPL2–IPL0 (normal mode), these input pins indicate the encoded priority level of the
external device requesting an interrupt. Level 7 is the highest (nonmaskable) priority;
whereas, level 0 indicates that no interrupt is requested. The least significant bit is IPL0,
and the most significant bit is IPL2. These lines must remain stable until the M68000 core
MOTOROLA
MC68LC302 REFERENCE MANUAL
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