MC68LC302 Datasheet, PDF (149/169 Pages) Motorola, Inc – Low Power Integrated Multiprotocol Processor Reference Manual

Electrical Characteristics
6.20 AC ELECTRICAL SPECIFICATIONS—GCI TIMING
GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal
mode uses 512 kHz clock rate (256K bit rate). MUX mode uses 256 x n - 3088 kbs (clock
rate is data rate x 2). The ratio CLKO/L1CLK must be greater than 2.5/1 (see Figure 6-20).
16.67 MHz 20 MHz
25 MHz
Num.
Characteristic
Min Max Min Max Min Max ^Unit
L1CLK GCI Clock Frequency (Normal Mode) (see
Note 1)
— 512 — 512 —
512 kHz
280 L1CLK Clock Period Normal Mode (see Note 1)
1800 2100 1800 2100 1800 2100 ns
281 L1CLK Width Low/High Normal Mode
840 1450 840 1450 840 1450 ns
282 L1CLK Rise/Fall Time Normal Mode (see Note 4) — — — — — — ns
L1CLK (GCI Clock) Period (MUX Mode) (see Note 1) — 6.668 — 6.668 — 6.668 MHz
280 L1CLK Clock Period MUX Mode (see Note 1)
150 — 150 — 150 — ns
281 L1CLK Width Low MUX Mode
55 — 55 — 55 — ns
281A L1CLK Width High MUX Mode (see Note 5)
P+10 — P+10 — P+10 — ns
282 L1CLK Rise/Fall Time MUX Mode (see Note 4)
— — — — — — ns
283 L1SY1 Sync Setup Time to L1CLK Falling Edge
30 — 25 — 20 — ns
284 L1SY1 Sync Hold Time from L1CLK Falling Edge
50 — 42 — 34 — ns
285
L1TxD Active Delay (from L1CLK Rising Edge) (see
Note 2)
0 100
0 85
0 70 ns
286
L1TxD Active Delay (from L1SY1 Rising Edge) (see
Note 2)
0 100
0 85
0 70 ns
287 L1RxD Setup Time to L1CLK Rising Edge
20 — 17 — 14 — ns
288 L1RxD Hold Time from L1CLK Rising Edge
50 — 42 — 34 — ns
289 ^{Time Between Successive L1SY1in}
Normal ^{64 — 64 — 64 — L1CLK}
SCIT Mode _{192 — 192 — 192 — L1CLK}
290
SDS1–SDS2 Active Delay from L1CLK Rising Edge
(see Note 3)
10
90
10 75
7 60 ns
291
SDS1–SDS2 Active Delay from L1SY1 Rising Edge
(see Note 3)
10
90
10 75
7 60 ns
292
SDS1–SDS2 Inactive Delay from L1CLK Falling
Edge
10 90 10 75 7 60 ns
293 GCIDCL (GCI Data Clock) Active Delay
0 50
0 42
0 34 ns
NOTES:
1. The ratio CLKO/L1CLK must be greater than 2.5/1.
2. Condition CL = 150 pF. L1TD becomes valid after the L1CLK rising edge or L1SY1, whichever is later.
3. SDS1–SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.
4. Schmitt trigger used on input buffer.
5. Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
6-32
MC68LC302 REFERENCE MANUAL
MOTOROLA