PIC18F47J53 Datasheet, PDF (92/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
6.3.5 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and periph-
eral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and
Table 6-4 provide a list of these registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
The SFRs located between EB0h and
F5Fh are not part of the Access Bank.
Either BANKED instructions (using BSR) or
the MOVFF instruction should be used to
access these locations. When program-
ming in MPLAB^® C18, the compiler will
automatically use the appropriate
addressing mode.
TABLE 6-2: ACCESS BANK SPECIAL FUNCTION REGISTER MAP
Address
Name
Address
Name
Address Name Address Name Address
Name
FFFh
FFEh
FFDh
FFCh
FFBh
TOSU
TOSH
TOSL
STKPTR
PCLATU
FDFh
FDEh
FDDh
FDCh
FDBh
INDF2⁽¹⁾
POSTINC2⁽¹⁾
POSTDEC2⁽¹⁾
PREINC2⁽¹⁾
PLUSW2⁽¹⁾
FBFh
FBEh
FBDh
FBCh
FBBh
PSTR1CON
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
IPR1
PIR1
PIE1
RCSTA2
OSCTUNE
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
FFAh PCLATH
FDAh
FSR2H
FBAh CCP1CON
F9Ah T1GCON
F7Ah
TMR3L
FF9h
PCL
FD9h
FSR2L
FB9h PSTR2CON
F99h
IPR5
F79h
T3CON
FF8h TBLPTRU
FD8h STATUS
FB8h ECCP2AS
F98h
PIR5
F78h
TMR4
FF7h TBLPTRH
FD7h
TMR0H
FB7h ECCP2DEL
F97h T3GCON
F77h
PR4
FF6h TBLPTRL
FD6h
TMR0L
FB6h CCPR2H
F96h
TRISE
F76h
T4CON
FF5h
FF4h
TABLAT
PRODH
FD5h
FD4h
T0CON
—⁽⁵⁾
FB5h CCPR2L
FB4h CCP2CON
F95h
F94h
TRISD
TRISC
F75h
F74h
SSP2BUF
SSP2ADD⁽³⁾
FF3h
PRODL
FD3h OSCCON
FB3h CTMUCONH
F93h
TRISB
F73h SSP2STAT
FF2h INTCON
FD2h CM1CON
FB2h CTMUCONL
F92h
TRISA
F72h SSP2CON1
FF1h INTCON2
FD1h CM2CON
FB1h CTMUICON
F91h
PIE5
F71h SSP2CON2
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
INTCON3
INDF0⁽¹⁾
POSTINC0⁽¹⁾
POSTDEC0⁽¹⁾
PREINC0⁽¹⁾
PLUSW0⁽¹⁾
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
FB0h
FAFh
FAEh
FADh
FACh
FABh
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
IPR4
PIR4
PIE4
LATE⁽²⁾
LATD⁽²⁾
LATC
F70h
F6Fh
F6Eh
F6Dh
F6Ch
CMSTAT
PMADDRH^{(2, 4)}
PMADDRL^{(2, 4)}
PMDIN1H⁽²⁾
PMDIN1L⁽²⁾
F6Bh TXADDRL
FEAh
FSR0H
FCAh
T2CON
FAAh RCREG2
F8Ah
LATB
F6Ah TXADDRH
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FSR0L
WREG
INDF1⁽¹⁾
POSTINC1⁽¹⁾
POSTDEC1⁽¹⁾
PREINC1⁽¹⁾
PLUSW1⁽¹⁾
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
SSP1BUF
SSP1ADD⁽³⁾
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
TXREG2
TXSTA2
EECON2
EECON1
IPR3
PIR3
PIE3
F89h
LATA
F88h DMACON1
F87h OSCCON2⁽⁵⁾
F86h DMACON2
F85h
F84h
F83h
HLVDCON
PORTE⁽²⁾
PORTD⁽²⁾
F69h
F68h
F67h
F66h
F65h
F64h
F63h
RXADDRL
RXADDRH
DMABCL
DMABCH
UCON
USTAT
UEIR
FE2h
FSR1H
FC2h ADCON0
FA2h
IPR2
F82h PORTC
F62h
UIR
FE1h
FSR1L
FC1h ADCON1
FA1h
PIR2
F81h PORTB
F61h
UFRMH
FE0h
BSR
FC0h WDTCON
FA0h
PIE2
F80h PORTA
F60h
UFRML
Note 1:
2:
3:
4:
5:
This is not a physical register.
This register is not available on 28-pin devices.
SSPxADD and SSPxMSK share the same address.
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
Reserved: Do not write to this location.
DS39964B-page 92
Preliminary
 2010 Microchip Technology Inc.