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PIC18F47J53 Datasheet, PDF (452/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology
PIC18F47J53 FAMILY
REGISTER 28-11: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ACCESS FC0h)
R/W-1
REGSLP
bit 7
R-x
LVDSTAT(2)
R-x
ULPLVL
R/W-0
VBGOE
R/W-0
DS(2)
R/W-0
ULPEN
R/W-0
ULPSINK
R/W-0
SWDTEN(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
bit 6
LVDSTAT: Low-Voltage Detect Status bit(2)
1 = VDDCORE > 2.45V nominal
0 = VDDCORE < 2.45V nominal
bit 5
ULPLVL: Ultra Low-Power Wake-up Output bit (not valid unless ULPEN = 1)
1 = Voltage on RA0 > ~0.5V
0 = Voltage on RA0 < ~0.5V
bit 4
VBGOE: Band Gap Reference Voltage (VBG) Output Enable bit
1 = Band gap reference output is enabled on pin RA1
0 = Band gap reference output is disabled
bit 3
DS: Deep Sleep Wake-up Status bit (used in conjunction with RCON, POR and BOR bits to determine
Reset source)(2)
1 = If the last exit from Reset was caused by a normal wake-up from Deep Sleep
0 = If the last exit from Reset was not due to a wake-up from Deep Sleep
bit 2
ULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = Ultra low-power wake-up module is enabled; ULPLVL bit indicates the comparator output
0 = Ultra low-power wake-up module is disabled
bit 1
ULPSINK: Ultra Low-Power Wake-up Current Sink Enable bit
1 = Ultra low-power wake-up current sink is enabled (if ULPEN = 1)
0 = Ultra low-power wake-up current sink is disabled
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
2: Not available on devices where the on-chip voltage regulator is disabled (“LF” devices).
TABLE 28-3: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCON
IPEN
—
CM
RI
TO
PD
POR
WDTCON
REGSLP LVDSTAT ULPLVL VBGOE
DS
ULPEN ULPSINK
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Bit 0
BOR
SWDTEN
DS39964B-page 452
Preliminary
 2010 Microchip Technology Inc.