PIC18F47J53 Datasheet, PDF (138/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CCP10IP
CCP9IP
CCP8IP
CCP7IP
CCP6IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits
1 = High priority
0 = Low priority
CCP3IP: ECCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
REGISTER 9-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 (ACCESS F99h)
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
CM3IP
TMR8IP
TMR6IP
TMR5IP TMR5GIP TMR1GIP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CM3IP: Comparator3 Interrupt Priority bit
1 = High priority
0 = Low priority
TMR8IP: TMR8 to PR8 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 = High priority
0 = Low priority
TMR5IP: TMR5 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
TMR5GIP: TMR5 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
TMR1GIP: TMR1 Gate Interrupt Priority bit
1 = High priority
0 = Low priority
DS39964B-page 138
Preliminary
 2010 Microchip Technology Inc.