PIC18F47J53 Datasheet, PDF (86/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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6.2 PIC18 Instruction Cycle
6.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by ‘4’ to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the PC is incremented on
every Q1; the instruction is fetched from the program
memory and latched into the Instruction Register (IR)
during Q4. The instruction is decoded and executed
during the following Q1 through Q4. Figure 6-4
illustrates the clocks and instruction execution flow.
6.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the PC to change (e.g., GOTO), then
two cycles are required to complete the instruction
(Example 6-3).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the IR in cycle, Q1. This instruction is then decoded
and executed during the Q2, Q3 and Q4 cycles. Data
memory is read during Q2 (operand read) and written
during Q4 (destination write).
FIGURE 6-4:
CLOCK/INSTRUCTION CYCLE
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
Q1 Q2 Q3 Q4
PC
Execute INST (PC – 2)
Fetch INST (PC)
Q1 Q2 Q3 Q4
PC + 2
Execute INST (PC)
Fetch INST (PC + 2)
Q1 Q2 Q3 Q4
PC + 4
Execute INST (PC + 2)
Fetch INST (PC + 4)
Internal
Phase
Clock
EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
TCY0
Fetch 1
TCY1
Execute 1
Fetch 2
3. BRA SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
TCY2
Execute 2
Fetch 3
TCY3
TCY4
TCY5
Execute 3
Fetch 4 Flush (NOP)
Fetch SUB_1 Execute SUB_1
Note:
All instructions are single-cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
DS39964B-page 86
Preliminary
 2010 Microchip Technology Inc.