PIC18F47J53 Datasheet, PDF (5/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Pin Diagrams
28-Pin QFN
PIC18F47J53 FAMILY
RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF
RA3/AN3/C1INB/VREF+
VDDCORE/VCAP
RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2
VSS1
OSC1/CLKI/RA7
OSC2/CLKO/RA6
28 27 26 25 24 23 22
1
21
2
20
3
4
PIC18F2XJ53
19
18
5
17
6
16
7
15
8 9 10 11 12 13 14
RB3/AN9/C3INA/CTED2/VPO/RP6
RB2/AN8/C2INC/CTED1/VMO/REFO/RP5
RB1/AN10/C3INC/RTCC/RP4
RB0/AN12/C3IND/INT0/RP3
VDD
VSS2
RC7/CCP10/RX1/DT1/SDO1/RP18
28-Pin SPDIP/SOIC/SSOP
MCLR
1
RA0/AN0/C1INA/ULPWU/RP0
2
RA1/AN1/C2INA/VBG/RP1
3
RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF
4
RA3/AN3/C1INB/VREF+
5
VDDCORE/VCAP
6
RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2
7
VSS1
8
OSC1/CLKI/RA7
9
OSC2/CLKO/RA6 10
RC0/T1OSO/T1CKI/RP11 ¹¹
RC1/CCP8/T1OSI/UOE/RP12 12
RC2/AN11/C2IND/CTPLS/RP13 13
VUSB 14
28 RB7/CCP7/KBI3/PGD/RP10
27 RB6/CCP6/KBI2/PGC/RP9
26 RB5/CCP5/KBI1/SDI1/SDA1/RP8
25 RB4/CCP4/KBI0/SCK1/SCL1/RP7
24 RB3/AN9/C3INA/CTED2/VPO/RP6
23 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5
22 RB1/AN10/C3INC/RTCC/RP4
21 RB0/AN12/C3IND/INT0/RP3
20 VDD
19 VSS2
18 RC7/CCP10/RX1/DT1/SDO1/RP18
17 RC6/CCP9/TX1/CK1/RP17
16 RC5/D+/VP
15 RC4/D-/VM
Legend:
Note:
Shaded pins are 5.5V tolerant.
RPn represents remappable pins. Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS mod-
ule, see Section 10.7 “Peripheral Pin Select (PPS)”.
For the QFN package, it is recommended that the bottom pad be connected to VSS.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 5