PIC18F47J53 Datasheet, PDF (54/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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4.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the internal
oscillator block. This mode allows for controllable
power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTOSC block, the primary
oscillator is shutdown and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the internal oscillator block. After a
delay of TCSD following the wake event, the CPU
begins executing code being clocked by the INTRC.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the FSCM is enabled.
4.5 Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval, TCSD, following the wake
event, is required when leaving Sleep mode. This delay
is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
4.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is, when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 28.2 “Watchdog
Timer (WDT)”).
The WDT and postscaler are cleared by one of the
following events:
• Executing a SLEEP or CLRWDT instruction
• The loss of a currently selected clock source (if
the FSCM is enabled)
4.5.3 EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
DS39964B-page 54
Preliminary
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