PIC18F47J53 Datasheet, PDF (59/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
R/W-xxxx⁽¹⁾
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.
REGISTER 4-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
R/W-xxxx⁽¹⁾
Deep Sleep Persistent General Purpose bits
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the
DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.
REGISTER 4-5:
U-0
—
bit 7
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
DSINT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 59