PIC18F47J53 Datasheet, PDF (413/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
24.7 Comparator Operation During
Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
24.8 Effects of a Reset
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
PIR5
PIE2
PIE5
IPR2
IPR5
CMxCON
CVRCON
CMSTAT
ANCON0
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIF
CM2IF
CM1IF
—
—
CM3IF
OSCFIE
CM2IE
CM1IE
—
—
CM3IE
OSCFIP
CM2IP
CM1IP
—
—
CM3IP
CON
COE
CPOL
CVREN CVROE
CVRR
—
—
—
PCFG7^(Leg PCFG6^(Leg- PCFG5^(Le
end:)
end:)
gend:)
INT0IE
USBIF
TMR8IF
USBIE
TMR8IE
USBIP
TMR8IP
EVPOL1
CVRSS
—
PCFG4
RBIE
BCL1IF
TMR6IF
BCL1IE
TMR6IE
BCL1IP
TMR6IP
EVPOL0
CVR3
—
PCFG3
TMR0IF
HLVDIF
TMR5IF
HLVDIE
TMR5IE
HLVDIP
TMR5IP
CREF
CVR2
COUT3
PCFG2
INT0IF
TMR3IF
TMR5GIF
TMR3IE
TMR5GIE
TMR3IP
TMR5GIP
CCH1
CVR1
COUT2
PCFG1
RBIF
CCP2IF
TMR1GIF
CCP2IE
TMR1GIE
CCP2IP
TMR1GIP
CCH0
CVR0
COUT1
PCFG0
ANCON1
VBGEN
—
—
PCFG12 PCFG11 PCFG10 PCFG9
TRISA
TRISA7 TRISA6 TRISA5
—
TRISA3 TRISA2 TRISA1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not related to comparator operation.
PCFG8
TRISA0
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 413