PIC18F47J53 Datasheet, PDF(159/586 Page) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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PIC18F47J53 Datasheet, PDF (159/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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PIC18F47J53 FAMILY

TABLE 10-11: PORTE I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

I/O

Type

Description

RE0/AN5/

PMRD

RE0

1

I

ST PORTE<0> data input; disabled when analog input is enabled.

0

O DIG LATE<0> data output; not affected by analog input.

AN5

1

I ANA A/D Input Channel 5; default input configuration on POR.

PMRD

1

I ST/TTL Parallel Master Port (io_rd_in).

0

O DIG Parallel Master Port read strobe.

RE1/AN6/

PMWR

RE1

1

I

ST PORTE<1> data input; disabled when analog input is enabled.

0

O DIG LATE<1> data output; not affected by analog input.

AN6

1

I ANA A/D Input Channel 6; default input configuration on POR.

PMWR

1

I ST/TTL Parallel Master Port (io_wr_in).

0

O DIG Parallel Master Port write strobe.

RE2/AN7/

PMCS

RE2

1

I

ST PORTE<2> data input; disabled when analog input is enabled.

0

O DIG LATE<2> data output; not affected by an analog input.

AN7

1

I ANA A/D Input Channel 7; default input configuration on POR.

PMCS

0

O DIG Parallel Master Port byte enable.

VSS1

VSS2

â

â

P

â Ground reference for logic and I/O pins.

AVSS1

â

â

P

â Ground reference for analog modules.

VDD1

VDD2

â

â

P

â Positive supply for peripheral digital logic and I/O pins.

VDDCORE/VCAP VDDCORE â

P

â Positive supply for microcontroller core logic (regulator disabled).

VCAP

â

P

â External filter capacitor connection (regulator enabled).

AVDD1

AVDD2

P

â

â

â Positive supply for analog modules.

â

VUSB

â

â

P

â USB voltage input pin.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level

I = Input; O = Output; P = Power

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

PORTE(1)

LATE(1)

TRISE(1)

ANCON0

â

â

RDPU

PCFG7(1)

â

â

REPU

PCFG6(1)

â

â

â

PCFG5(1)

â

â

â

PCFG4

â

â

â

PCFG3

RE2

LATE2

TRISE2

PCFG2

RE1

LATE1

TRISE1

PCFG1

Legend: â = unimplemented, read as â0â. Shaded cells are not used by PORTE.

Note 1: These registers and/or bits are not available in 28-pin devices (PIC18F26J53, PIC18F27J53,

PIC18LF26J53 and PIC18LF26J53).

Bit 0

RE0

LATE0

TRISE0

PCFG0

Note:

bit 7 RDPU: PORTD Pull-up Enable bit

0 = All PORTD pull-ups are disabled

1 = PORTD pull-ups are enabled for any input pad

bit 6 REPU: PORTE Pull-up Enable bit

0 = All PORTE pull-ups are disabled

1 = PORTE pull-ups are enabled for any input pad

ï£ 2010 Microchip Technology Inc.

Preliminary

DS39964B-page 159

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