PIC18F47J53 Datasheet, PDF (365/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
21.4 EUSART Synchronous Slave
Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is sup-
plied externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
21.4.1 EUSART SYNCHRONOUS SLAVE
TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx, and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second word
to the TSR and flag bit, TXxIF, will now be set.
e) If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 21-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽¹⁾
PMPIE⁽¹⁾
PMPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
PIR3
SSP2IF BCL2IF
RC2IF
TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3
SSP2IE BCL2IE RC2IE
TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3
SSP2IP BCL2IP RC2IP
TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
TXREGx
EUSARTx Transmit Register
TXSTAx
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE
ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx
EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: These pins are only available on 44-pin devices.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 365