PIC18F47J53 Datasheet, PDF (329/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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20.5.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I²C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I²C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit), the
SSPxIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPxADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPxSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary. The UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 20-17).
FIGURE 20-17:
SDAx
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7-BIT OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address
after ACK, set interrupt
General Call Address
R/W = 0
Receiving Data
ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
SSPxIF
S
1 2 34 5 6 78 91 2 34 5 6 78 9
BF (SSPxSTAT<0>)
SSPOV (SSPxCON1<6>)
GCEN (SSPxCON2<7>)
Cleared in software
SSPxBUF is read
‘0’
‘1’
20.5.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Start (S) and Stop (P) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I²C bus may be taken when the Stop bit is set, or
the bus is Idle, with both the Start and Stop bits clear.
In Firmware Controlled Master mode, user code
conducts all I²C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDAx and SCLx.
2. Assert a Repeated Start condition on SDAx and
SCLx.
3. Write to the SSPxBUF register initiating
transmission of data/address.
4. Configure the I²C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDAx and SCLx.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 329