PIC18F47J53 Datasheet, PDF (148/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
10.3 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-3: INITIALIZING PORTB
CLRF
CLRF
MOVLW
MOVFF
PORTB
; Initialize PORTB by
; clearing output
; data latches
LATB
; Alternate method
; to clear output
; data latches
0x3F
; Configure as digital I/O
WREG ADCON1 ; pins in this example
MOVLW 0CFh
MOVWF TRISB
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a POR. The integrated weak pull-ups
consist of a semiconductor structure similar to, but
somewhat different from, a discrete resistor. On an
unloaded I/O pin, the weak pull-ups are intended to
provide logic high indication, but will not necessarily
pull the pin all the way to VDD levels.
Note:
On a POR, the RB<3:0> bits are
configured as analog inputs by default and
read as ‘0’; RB<7:4> bits are configured
as digital inputs.
Four of the PORTB pins (RB<7:4>) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep mode or
any of the Idle modes. Application software can clear
the interrupt flag by following these steps:
1. Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction).
2. Wait one instruction cycle (such as executing a
NOP instruction).
3. Clear flag bit, RBIF.
A mismatch condition continues to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one instruction
cycle of delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB5 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RB5/CCP5/KBI1/SDI1/SDA1/RP8 pin.
DS39964B-page 148
Preliminary
 2010 Microchip Technology Inc.