PIC18F47J53 Datasheet, PDF (226/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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15.3 Timer3/5 16-Bit Read/Write Mode
Timer3/5 can be configured for 16-bit reads and writes
(see Figure 15.3). When the RD16 control bit
(TxCON<1>) is set, the address for TMRxH is mapped to
a buffer register for the high byte of Timer3/5. A read from
TMRxL will load the contents of the high byte of Timer3/5
into the Timerx High Byte Buffer register. This provides
users with the ability to accurately read all 16 bits of
Timer3/5 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3/5 must also take place
through the TMRxH Buffer register. The Timer3/5 high
byte is updated with the contents of TMRxH when a write
occurs to TMRxL. This allows users to write all 16 bits to
both the high and low bytes of Timer3/5 at once.
The high byte of Timer3/5 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timerx High Byte Buffer register.
Writes to TMRxH do not clear the Timer3/5 prescaler.
The prescaler is only cleared on writes to TMRxL.
15.4 Using the Timer1 Oscillator as the
Timer3/5 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3/5. The Timer1 oscillator is enabled
by setting the T1OSCEN (T1CON<3>) bit. To use it as
the Timer3/5 clock source, the TMRxCS bits must also
be set. As previously noted, this also configures
Timer3/5 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
15.5 Timer3/5 Gates
Timer3/5 can be configured to count freely or the count
can be enabled and disabled using the Timer3/5 gate
circuitry. This is also referred to as the Timer3/5 gate
count enable.
The Timer3/5 gate can also be driven by multiple
selectable sources.
15.5.1 TIMER3/5 GATE COUNT ENABLE
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5
will increment on the rising edge of the Timer3/5 clock
source. When Timerx Gate Enable mode is disabled,
no incrementing will occur and Timer3/5 will hold the
current count. See Figure 15-2 for timing details.
TABLE 15-1: TIMER3/5 GATE ENABLE
SELECTIONS
TxCLK^(†)
TxGPOL
(TxGCON<6>)
TxG
Pin
Timerx
Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
† The clock on which TMR3/5 is running. For more
information, see TxCLK in Figure 15-1.
FIGURE 15-2:
TMRxGE
TIMER3/5 GATE COUNT ENABLE MODE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5
N
N+1
N+2
N+3
N+4
DS39964B-page 226
Preliminary
 2010 Microchip Technology Inc.