PIC18F47J53 Datasheet, PDF (344/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 20-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽³⁾
PMPIE⁽³⁾
PMPIP⁽³⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
PIR2
OSCFIF
CM2IF
CM1IF
USBIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CM2IE
CM1IE
USBIE
BCL1IE HLVDIE TMR3IE CCP2IE
IPR2
OSCFIP
CM2IP
CM1IP
USBIP
BCL1IP HLVDIP TMR3IP CCP2IP
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP CTMUIP TMR3GIP RTCCIP
TRISC
TRISC7 TRISC6
—
—
—
TRISC2 TRISC1 TRISC0
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
SSP1BUF
SSP1ADD
SSPxMSK⁽¹⁾
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I²C™ Slave mode), MSSP1 Baud Rate Reload Register (I²C Master mode)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
SSPxCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPxCON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
ACKSTAT ADMSK5⁽²⁾ ADMSK4⁽²⁾ ADMSK3⁽²⁾ ADMSK2⁽²⁾ ADMSK1⁽²⁾
SEN
SEN
SSPxSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I²C Slave mode), MSSP2 Baud Rate Reload Register (I²C Master mode)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSPx module in I²C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I²C Slave
mode operations in 7-Bit Masking mode. See Section 20.5.3.4 “7-Bit Address Masking Mode” for more
details.
2: Alternate bit definitions for use in I²C Slave mode operations only.
3: These bits are only available on 44-pin devices.
DS39964B-page 344
Preliminary
 2010 Microchip Technology Inc.