PIC18F47J53 Datasheet, PDF (307/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
20.4.6 USING THE SPI DMA MODULE
The following steps would typically be taken to enable
and use the SPI DMA module:
1. Configure the I/O pins, which will be used by
MSSP2.
a) Assign SCK2, SDO2, SDI2 and SS2 to the
RPn pins as appropriate for the SPI mode
which will be used. Only functions which will
be used need to be assigned to a pin.
b) Initialize the associated LATx registers for
the desired Idle SPI bus state.
c) If Open-Drain Output mode on SDO2 and
SCK2 (Master mode) is desired, set
ODCON3<1>.
d) Configure corresponding TRISx bits for
each I/O pin used.
2. Configure and enable MSSP2 for the desired
SPI operating mode.
a) Select the desired operating mode (Master
or Slave, SPI Mode 0, 1, 2 and 3) and con-
figure the module by writing to the
SSP2STAT and SSP2CON1 registers.
b) Enable MSSP2 by setting SSP2CON1<5> = 1.
3. Configure the SPI DMA engine.
a) Select the desired operating mode by
writing the appropriate values to
DMACON2 and DMACON1.
b) Initialize the TXADDRH/TXADDRL Pointer
(Full-Duplex or Half-Duplex Transmit Only
mode).
c) Initialize the RXADDRH/RXADDRL Pointer
(Full-Duplex or Half-Duplex Receive Only
mode).
d) Initialize the DMABCH/DMABCL Byte Count
register with the number of bytes to be
transferred in the next SPI DMA operation.
e) Set the DMAEN bit (DMACON1<0>).
In SPI Master modes, this will initiate a DMA
transaction. In SPI Slave modes, this will
complete the initialization process, and the
module will now be ready to begin receiving
and/or transmitting data to the master
device once the master starts the
transaction.
4. Detect the SSP2IF interrupt condition (PIR3<7).
a) If the interrupt was configured to occur at
the completion of the SPI DMA transaction,
the DMAEN bit (DMACON1<0>) will be
clear. User firmware may prepare the
module for another transaction by repeating
steps 3.b through 3.e.
b) If the interrupt was configured to occur prior
to the completion of the SPI DMA trans-
action, the DMAEN bit may still be set,
indicating the transaction is still in progress.
User firmware would typically use this inter-
rupt condition to begin preparing new data
for the next DMA transaction. Firmware
should not repeat steps 3.b. through 3.e.
until the DMAEN bit is cleared by the
hardware, indicating the transaction is
complete.
Example 20-2 provides example code demonstrating
the initialization process and the steps needed to use
the SPI DMA module to perform a 512-byte Full-Duplex
Master mode transfer.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 307