PIC18F47J53 Datasheet, PDF (36/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
FIGURE 3-1:
PIC18F47J53 FAMILY CLOCK DIAGRAM
PLLDIV<2:0>
OSC2
Primary Oscillator
OSC1
FOSC2
1
0
PLLEN
CFGPLLEN
 12
 10
6
5
4
3
2
1
000
001
010
011
100
101
110
111
4 MHz 96 MHz
PLL⁽¹⁾
 2 ^{48 MHz}
FSEN
1
(Note 2)
0
CPDIV<1:0>
8 1
4 ⁰
1
USB Module
Clock
Needs 48 MHz for FS
Needs 6 MHz for LS
0
6
00
3
01
2
10
1
11
FOSC<2:1>
LS48MHZ
T1OSO
Secondary Oscillator
T1OSI
Internal
Oscillator
Block
8 MHz
INTRC
31 kHz
8 MHz
OSCCON<6:4>
8 MHz
4 MHz ¹¹¹
110
2 MHz
101
1 MHz
100
500 kHz
011
250 kHz
010
125 kHz
001
1 31 kHz
000
0
OSCTUNE<7>
Primary Clock
Source⁽⁴⁾
IDLE
CPU
00
00
Timer1 Clock⁽³⁾
01
Peripherals
Postscaled
11
Internal Clock
4
OSCCON<1:0> _CLKO
Enabled Modes
RA6
WDT, PWRT, FSCM
and Two-Speed Start-up
Note 1:
2:
3:
4:
The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit
in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to t_rc to lock. During this time, the
device continues to be clocked at the PLL bypassed frequency.
In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this
node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.
Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 3.6 “Reference Clock Output”) and PLL.
The USB module cannot be used to communicate unless the primary clock source is selected.
DS39964B-page 36
Preliminary
 2010 Microchip Technology Inc.