PIC18F47J53 Datasheet, PDF(149/586 Page) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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PIC18F47J53 Datasheet, PDF (149/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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PIC18F47J53 FAMILY

TABLE 10-5: PORTB I/O SUMMARY

Pin

Function

TRIS

Setting

I/O

I/O

Type

Description

RB0/AN12/

RB0

1

I

TTL PORTB<0> data input; weak pull-up when the RBPU bit is

C3IND/INT0/

cleared. Disabled when analog input is enabled.(1)

RP3

0

O DIG LATB<0> data output; not affected by analog input.

AN12

1

I

ANA A/D Input Channel 12.(1)

C3IND

1

I ANA Comparator 3 Input D.

INT0

1

I

ST External Interrupt 0 input.

RP3

1

I

ST Remappable Peripheral Pin 3 input.

0

O DIG Remappable Peripheral Pin 3 output.

RB1/AN10/

RB1

1

I

TTL PORTB<1> data input; weak pull-up when the RBPU bit is

C3INC/PMBE/

cleared. Disabled when analog input is enabled.(1)

RTCC/

RP4

0

O DIG LATB<1> data output; not affected by analog input.

AN10

1

I

ANA A/D Input Channel 10.(1)

C3INC

1

PMBE(3)

x

I ANA Comparator 3 Input C.

O DIG Parallel Master Port byte enable.

RTCC

0

O DIG Asynchronous serial transmit data output (USART module).

RP4

1

I

ST Remappable Peripheral Pin 4 input.

0

O DIG Remappable Peripheral Pin 4 output.

RB2/AN8/

RB2

C2INC/CTED1/

PMA3/VMO/

REFO/RP5

AN8

1

I

TTL PORTB<2> data input; weak pull-up when the RBPU bit is

cleared. Disabled when analog input is enabled.(1)

0

O DIG LATB<2> data output; not affected by analog input.

1

I

ANA A/D Input Channel 8.(1)

C2INC

1

I ANA Comparator 2 Input C.

CTED1

1

PMA3(3)

x

I

ST CTMU Edge 1 input.

O DIG Parallel Master Port address.

VMO

0

O DIG External USB transceiver D- data output.

REFO

0

O DIG Reference output clock.

RP5

1

I

ST Remappable Peripheral Pin 5 input.

0

O DIG Remappable Peripheral Pin 5 output.

RB3/AN9/

RB3

C3INA/CTED2/

PMA2/VPO/

RP6

AN9

0

O DIG LATB<3> data output; not affected by analog input.

1

I

TTL PORTB<3> data input; weak pull-up when the RBPU bit is

cleared. Disabled when analog input is enabled.(1)

1

I

ANA A/D Input Channel 9.(1)

C3INA

1

I ANA Comparator 3 Input A.

CTED2

1

PMA2(3)

x

I

ST CTMU Edge 2 input.

O DIG Parallel Master Port address.

VPO

0

O DIG External USB transceiver D+ data output.

RP6

1

I

ST Remappable Peripheral Pin 6 input.

0

O DIG Remappable Peripheral Pin 6 output.

Legend:

Note 1:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level

input/output; x = Donât care (TRIS bit does not affect port direction or is overridden for this option)

Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting

the appropriate bits in the ANCON1 register.

2: All other pin functions are disabled when ICSPâ¢ or ICD is enabled.

3: Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).

ï£ 2010 Microchip Technology Inc.

Preliminary

DS39964B-page 149

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