PIC18F47J53 Datasheet, PDF (314/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
REGISTER 20-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I²C™ SLAVE MODE)
(1, ACCESS FC5h; 2, F71h)
R/W-0
GCEN
bit 7
R/W-0
ACKSTAT⁽²⁾
R/W-0
ADMSK5
R/W-0
ADMSK4
R/W-0
ADMSK3
R/W-0
ADMSK2
R/W-0
ADMSK1
R/W-0
SEN⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-2
bit 1
bit 0
GCEN: General Call Enable bit (Slave mode only)
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit⁽²⁾
Unused in Slave mode.
ADMSK<5:2>: Slave Address Mask Select bits (5-bit address masking)
1 = Masking of the corresponding bits of SSPxADD are enabled
0 = Masking of the corresponding bits of SSPxADD are disabled
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SSPxADD<1> only enabled
0 = Masking of SSPxADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPxADD<1:0> enabled
0 = Masking of SSPxADD<1:0> disabled
SEN: Start Condition Enable/Stretch Enable bit⁽¹⁾
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
2:
If the I²C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
This bit is unimplemented in I²C Slave mode.
REGISTER 20-9: SSPxMSK: I²C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
(1, ACCESS FC8h; 2, F74h)⁽¹⁾
R/W-1
MSK7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0⁽²⁾
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MSK<7:0>: Slave Address Mask Select bits
1 = Masking of the corresponding bit of SSPxADD is enabled
0 = Masking of the corresponding bit of SSPxADD is disabled
Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSP
operating modes. See Section 20.5.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
DS39964B-page 314
Preliminary
 2010 Microchip Technology Inc.