PIC18F47J53 Datasheet, PDF (288/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
FIGURE 19-16:
STRA⁽²⁾
PxA Signal
CCPxM1
PORT Data⁽¹⁾
STRB⁽²⁾
SIMPLIFIED STEERING
BLOCK DIAGRAM
Output Pin
1
0
TRIS
CCPxM0
PORT Data⁽¹⁾
STRC⁽²⁾
1
Output Pin
0
TRIS
CCPxM1
PORT Data⁽¹⁾
STRD⁽²⁾
1
Output Pin
0
TRIS
CCPxM0
1
Output Pin
PORT Data⁽¹⁾
0
TRIS
Note 1:
2:
Port outputs are configured as displayed when
the CCPxCON register bits, PxM<1:0> = 00
and CCP1M<3:2> = 11.
Single PWM output requires setting at least
one of the STR<D:A> bits.
19.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTRxCON register gives the
user two choices for when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the out-
put signal at the Px<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figure 19-17 and Figure 19-18 illustrate the timing
diagrams of the PWM steering depending on the
STRSYNC setting.
FIGURE 19-17:
PWM
STRn
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
PWM Period
P1<D:A>
PORT Data
P1n = PWM
PORT Data
FIGURE 19-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
PWM
STRn
P1<D:A>
PORT Data
P1n = PWM
PORT Data
DS39964B-page 288
Preliminary
 2010 Microchip Technology Inc.