PIC18F47J53 Datasheet, PDF (581/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ...................................................... 322
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 323
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 328
I²C Slave Mode (10-Bit Transmission)...................... 324
I²C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011).............................................. 320
I²C Slave Mode (7-Bit Reception, SEN = 0) ............. 319
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 327
I²C Slave Mode (7-Bit Transmission)........................ 321
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode)......... 329
I²C Stop Condition Receive or Transmit Mode ......... 338
Low-Voltage Detect (VDIRMAG = 0) ........................ 422
MSSPx I²C Bus Data ................................................ 548
MSSPx I²C Bus Start/Stop Bits................................. 548
Parallel Master Port Read......................................... 540
Parallel Master Port Write ......................................... 541
Parallel Slave Port Read................................... 189, 191
Parallel Slave Port Write ................................... 189, 192
PWM Auto-Shutdown with Auto-Restart Enabled..... 284
PWM Auto-Shutdown with Firmware Restart............ 284
PWM Direction Change ............................................ 281
PWM Direction Change at Near 100%
Duty Cycle................................................................. 282
PWM Output ............................................................. 266
PWM Output (Active-High)........................................ 276
PWM Output (Active-Low) ........................................ 277
Read and Write, 8-Bit Data, Demultiplexed
Address............................................................. 196
Read, 16-Bit Data, Demultiplexed Address .............. 199
Read, 16-Bit Multiplexed Data, Fully Multiplexed
16-Bit Address .................................................. 200
Read, 16-Bit Multiplexed Data, Partially
Multiplexed Address ......................................... 199
Read, 8-Bit Data, Fully Multiplexed
16-Bit Address .................................................. 198
Read, 8-Bit Data, Partially Multiplexed Address ....... 196
Read, 8-Bit Data, Partially Multiplexed Address,
Enable Strobe ................................................... 197
Read, 8-Bit Data, Wait States Enabled, Partially
Multiplexed Address.................................................. 196
Repeated Start Condition.......................................... 334
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT)................................................... 537
Send Break Character Sequence ............................. 360
Slave Synchronization .............................................. 298
Slow Rise Time (MCLR Tied to VDD, VDD
Rise > TPWRT)............................................................. 69
SPI Mode (Master Mode).......................................... 297
SPI Mode (Slave Mode, CKE = 0) ............................ 299
SPI Mode (Slave Mode, CKE = 1) ............................ 299
Steering Event at Beginning of Instruction
(STRSYNC = 1) ................................................ 288
Steering Event at End of Instruction
(STRSYNC = 0) ........................................................ 288
Synchronous Reception (Master Mode, SREN) ....... 363
Synchronous Transmission....................................... 361
Synchronous Transmission (Through TXEN) ........... 362
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 1 .................................... 69
Time-out Sequence on Power-up (MCLR
Not Tied to VDD), Case 2 ............................................ 69
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ........................ 68
Timer Pulse Generation............................................ 254
Timer0 and Timer1 External Clock ........................... 538
Timer1 Gate Count Enable Mode............................. 215
Timer1 Gate Single Pulse Mode............................... 217
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 218
Timer1 Gate Toggle Mode........................................ 216
Timer3 Gate Count Enable Mode............................. 226
Timer3 Gate Single Pulse Mode............................... 228
Timer3 Gate Single Pulse/Toggle
Combined Mode ....................................................... 229
Timer3 Gate Toggle Mode........................................ 227
Transition for Entry to Idle Mode ................................ 53
Transition for Entry to SEC_RUN Mode ..................... 49
Transition for Entry to Sleep Mode ............................. 51
Transition for Two-Speed Start-up
(INTRC to HSPLL)............................................ 455
Transition for Wake From Idle to Run Mode............... 53
Transition for Wake From Sleep (HSPLL) .................. 51
Transition From RC_RUN Mode to
PRI_RUN Mode.................................................. 50
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ........................................... 49
Transition to RC_RUN Mode...................................... 50
USB Signal ............................................................... 553
Write, 16-Bit Data, Demultiplexed Address .............. 199
Write, 16-Bit Multiplexed Data, Fully
Multiplexed 16-Bit Address............................... 200
Write, 16-Bit Multiplexed Data, Partially
Multiplexed Address ......................................... 200
Write, 8-Bit Data, Fully Multiplexed
16-Bit Address .................................................. 198
Write, 8-Bit Data, Partially Multiplexed Address ....... 197
Write, 8-Bit Data, Partially Multiplexed Address,
Enable Strobe................................................... 198
Write, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address ........................... 197
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy........................................ 535
CLKO and I/O Requirements.................................... 536
Enhanced Capture/Compare/PWM
Requirements ................................................... 540
EUSARTx Synchronous Receive Requirements...... 550
EUSARTx Synchronous Transmission
Requirements ........................................................... 550
Example SPI Mode Requirements (Master Mode,
CKE = 0)........................................................... 542
Example SPI Mode Requirements (Master Mode,
CKE = 1)........................................................... 543
Example SPI Mode Requirements (Slave Mode,
CKE = 0)........................................................... 544
Example SPI Slave Mode Requirements
(CKE = 1).................................................................. 545
External Clock Requirements ................................... 535
I²C Bus Data Requirements (Slave Mode) ............... 547
I²C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 546
MSSPx I²C Bus Data Requirements ........................ 549
MSSPx I²C Bus Start/Stop Bits Requirements......... 548
Parallel Master Port Read Requirements ................. 541
Parallel Master Port Write Requirements ................. 541
PLL Clock ................................................................. 535
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Preliminary
DS39964B-page 581