PIC18F47J53 Datasheet, PDF (134/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP10IE
CCP9IE
CCP8IE
CCP7IE
CCP6IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
CCP10IE:CCP4IE: CCP<10:4> Interrupt Enable bits
1 = Enabled
0 = Disabled
CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
REGISTER 9-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 (ACCESS F91h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CM3IE
TMR8IE
TMR6IE
TMR5IE TMR5GIE TMR1GIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
CM3IE: Comparator3 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR8IE: TMR8 to PR8 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR5IE: TMR5 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR5GIE: TMR5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR1GIE: TMR1 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
DS39964B-page 134
Preliminary
 2010 Microchip Technology Inc.