PIC18F47J53 Datasheet, PDF (265/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 18-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
PIR4
CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE4
CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR4
CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC
TRISC7 TRISC6
—
—
—
TRISC2 TRISC1 TRISC0
TRISE
RDPU
REPU
—
—
—
TRISE2 TRISE1 TRISE0
TMR1L
Timer1 Register Low Byte
TMR1H
Timer1 Register High Byte
TMR3L
Timer3 Register Low Byte
TMR3H
Timer3 Register High Byte
TMR5L
Timer5 Register Low Byte
TMR5H
Timer5 Register High Byte
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON
T3CON
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON
T5CON
TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 T5OSCEN T5SYNC RD16 TMR5ON
CCPR4L
CCPR4L7 CCPR4L6 CCPR4L5 CCPR4L4 CCPR4L3 CCPR4L2 CCPR4L1 CCPR4L0
CCPR4H
CCPR4H7 CCPR4H6 CCPR4H5 CCPR4H4 CCPR4H3 CCPR4H2 CCPR4H1 CCPR4H0
CCPR5L
CCPR5L7 CCPR5L6 CCPR5L5 CCPR5L4 CCPR5L3 CCPR5L2 CCPR5L1 CCPR5L0
CCPR5H
CCPR5H7 CCPR5H6 CCPR5H5 CCPR5H4 CCPR5H3 CCPR5H2 CCPR5H1 CCPR5H0
CCPR6L
CCPR6L7 CCPR6L6 CCPR6L5 CCPR6L4 CCPR6L3 CCPR6L2 CCPR6L1 CCPR6L0
CCPR6H
CCPR6H7 CCPR6H6 CCPR6H5 CCPR6H4 CCPR6H3 CCPR6H2 CCPR6H1 CCPR6H0
CCPR7L
CCPR7L7 CCPR7L6 CCPR7L5 CCPR7L4 CCPR7L3 CCPR7L2 CCPR7L1 CCPR7L0
CCPR7H
CCPR7H7 CCPR7H6 CCPR7H5 CCPR7H4 CCPR7H3 CCPR7H2 CCPR7H1 CCPR7H0
CCPR8L
CCPR8L7 CCPR8L6 CCPR8L5 CCPR8L4 CCPR8L3 CCPR8L2 CCPR8L1 CCPR8L0
CCPR8H
CCPR8H7 CCPR8H6 CCPR8H5 CCPR8H4 CCPR8H3 CCPR8H2 CCPR8H1 CCPR8H0
CCPR9L
CCPR9L7 CCPR9L6 CCPR9L5 CCPR9L4 CCPR9L3 CCPR9L2 CCPR9L1 CCPR9L0
CCPR9H
CCPR9H7 CCPR9H6 CCPR9H5 CCPR9H4 CCPR9H3 CCPR9H2 CCPR9H1 CCPR9H0
CCPR10L
CCPR10L7 CCPR10L6 CCPR10L5 CCPR10L4 CCPR10L3 CCPR10L2 CCPR10L1 CCPR10L0
CCPR10H
CCPR10H7 CCPR10H6 CCPR10H5 CCPR10H4 CCPR10H3 CCPR10H2 CCPR10H1 CCPR10H0
CCP4CON
—
—
DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0
CCP5CON
—
—
DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0
CCP6CON
—
—
DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0
CCP7CON
—
—
DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0
CCP8CON
—
—
DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0
CCP9CON
—
—
DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0
CCP10CON
—
—
DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCPTMRS1 C7TSEL1 C7TSEL0
—
C6TSEL0
—
C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS2
—
—
—
C10TSEL0
—
C9TSEL0 C8TSEL1 C8TSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 265