PIC18F47J53 Datasheet, PDF (378/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
22.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
EXAMPLE 22-1: SAMPLE A/D CALIBRATION ROUTINE
BCF
BSF
BSF
BSF
CALIBRATION
BTFSC
BRA
BCF
ANCON0,PCFG0
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
;Make Channel 0 analog
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
TABLE 22-2: SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽¹⁾
PMPIE⁽¹⁾
PMPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
PIR2
OSCFIF CM2IF
CM1IF
USBIF BCL1IF HLVDIF TMR3IF CCP2IF
PIE2
OSCFIE CM2IE
CM1IE
USBIE BCL1IE HLVDIE TMR3IE CCP2IE
IPR2
OSCFIP CM2IP
CM1IP
USBIP BCL1IP HLVDIP TMR3IP CCP2IP
ADCTRIG
—
—
—
—
—
— TRIGSEL1 TRIGSEL0
ADRESH
A/D Result Register High Byte
ADRESL
A/D Result Register Low Byte
ADCON0
ANCON0
VCFG1 VCFG0
CHS3
PCFG7⁽¹⁾ PCFG6⁽¹⁾ PCFG5⁽¹⁾
CHS3
PCFG4
CHS1
PCFG3
CHS0 GO/DONE ADON
PCFG2 PCFG1 PCFG0
ADCON1
ADFM
ADCAL
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
ANCON1
VBGEN
r
—
PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
CCP2CON
P2M1
P2M0
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
TRISA
TRISA7 TRISA6 TRISA5
—
TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion.
Note 1: These bits are only available on 44-pin devices.
DS39964B-page 378
Preliminary
 2010 Microchip Technology Inc.