PIC18F47J53 Datasheet, PDF (334/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
20.5.9
I²C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I²C logic
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the BRG is loaded with the contents of
SSPxADD<5:0> and begins counting. The SDAx pin is
released (brought high) for one BRG count (TBRG).
When the BRG times out, and if SDAx is sampled high,
the SCLx pin will be deasserted (brought high). When
SCLx is sampled high, the BRG is reloaded with the
contents of SSPxADD<6:0> and begins counting.
SDAx and SCLx must be sampled high for one TBRG.
This action is then followed by assertion of the SDAx
pin (SDAx = 0) for one TBRG while SCLx is high.
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the BRG will not be
reloaded, leaving the SDAx pin held low. As soon as a
Start condition is detected on the SDAx and SCLx pins,
the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit
will not be set until the BRG has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDAx is sampled low when SCLx
goes from low-to-high.
• SCLx goes low before SDAx is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional 8 bits
of address (10-bit mode) or 8 bits of data (7-bit mode).
20.5.9.1 WCOL Status Flag
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
Note:
Because queueing of events is not
allowed, writing of the lower five bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 20-22: REPEATED START CONDITION WAVEFORM
SDAx = 1,
Write to SSPxCON2 occurs here: SDAx = 1,
SCLx = 1
SCLx (no change).
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
TBRG TBRG TBRG
SDAx
1st bit
RSEN bit set by hardware
on falling edge of ninth clock,
end of XMIT
SCLx
Write to SSPxBUF occurs here
TBRG
TBRG
Sr = Repeated Start
DS39964B-page 334
Preliminary
 2010 Microchip Technology Inc.