PIC18F47J53 Datasheet, PDF (225/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
15.2 Timer3/5 Operation
Timer3 and Timer5 can operate in these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5 increments on every internal
instruction cycle (FOSC/4). When TMRxCSx = 01, the
Timer3/5 clock source is the system clock (FOSC), and
when it is ‘10’, Timer3/5 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the Timer1 oscillator.
FIGURE 15-1:
TIMER3/5 BLOCK DIAGRAM
TxGSS<1:0>
TxG
00
TxGSPM
From Timer4/6
01
Match PR4/6
Comparator 1
Output
10
Comparator 2
11
Output
TxGPOL
TxG_IN
TMRxON
TxGTM
DQ
CK ^Q
R
Set flag bit
TMRxIF on
Overflow
TMRx⁽²⁾
TMRxH
TMRxL
0
Single Pulse
Acq. Control
1
TxGGO/TxDONE
0
TxGVAL
DQ
1
Q1 EN
Interrupt
det
TMRxON
TMRxGE
EN
TxCLK
0
QD
Synchronized
Clock Input
Data Bus
RD
T3GCON
Set
TMRxGIF
1
T1OSO/T1CKI
OUT
TMRxCS<1:0>
TxSYNC
T1OSC/SOSC
Prescaler
Synchronize⁽³⁾
T1OSI
1
EN
1, 2, 4, 8
det
10
SOSCGO
2
T1OSCEN
T3OSCEN
T5OSCEN
TXOSCEN
0
FOSC
TxCKPS<1:0>
Internal ⁰¹
Clock
FOSC/2
Internal
Sleep Input
FOSC/4
Clock
Internal ⁰⁰
(1)
Clock
TxCKI
Note 1:
2:
3:
ST buffer is a high-speed type when using T1CKI.
Timerx registers increment on rising edge.
Synchronization does not operate while in Sleep.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 225