PIC18F47J53 Datasheet, PDF (552/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 31-31: 10-BIT A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
0.7 25.0⁽¹⁾ s TOSC based, VREF  3.0V
131 TCNV Conversion Time
(not including acquisition time)⁽²⁾
132 TACQ Acquisition Time⁽³⁾
11
12
TAD
1.4
—
s -40C to +85C
135 TSWC Switching Time from Convert  Sample
— (Note 4)
137 TDIS Discharge Time
0.2
—
s
Note 1:
2:
3:
4:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the con-
version (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50W.
On the following cycle of the device clock.
TABLE 31-32: 12-BIT A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
0.8 12.5⁽¹⁾ s TOSC based, VREF  3.0V
131 TCNV Conversion Time
(not including acquisition time)⁽²⁾
132 TACQ Acquisition Time⁽³⁾
13
14
TAD
1.4
—
s
135 TSWC Switching Time from Convert  Sample
— (Note 4)
137 TDIS Discharge Time
0.2
—
s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
DS39964B-page 552
Preliminary
 2010 Microchip Technology Inc.