PIC18F47J53 Datasheet, PDF (353/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
21.1.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 21-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
In ABD mode, the internal BRG is used as a counter to
time the bit period of the incoming serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The ABD must receive
a byte with the value, 55h (ASCII “U”, which is also the
LIN/J2602 bus Sync character), in order to calculate the
proper bit rate. The measurement is taken over both a
low and high bit time in order to minimize any effects
caused by asymmetry of the incoming signal. After a
Start bit, the SPBRGx begins counting up, using the pre-
selected clock source on the first rising edge of RXx.
After eight bits on the RXx pin, or the fifth rising edge, an
accumulated value totalling the proper BRG period is left
in the SPBRGHx:SPBRGx register pair. Once the 5^th
edge is seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCONx<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 21-2).
While calibrating the baud rate period, the BRG
registers are clocked at 1/8^th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRGx and SPBRGHx will be used
as a 16-bit counter. This allows the user to verify that
no carry occurred for 8-bit modes by checking for 00h
in the SPBRGHx register.
Refer to Table 21-4 for counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCxIF interrupt is set
once the fifth rising edge on RXx is detected. The value
in the RCREGx needs to be read to clear the RCxIF
interrupt. The contents of RCREGx should be
discarded.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
TABLE 21-4: BRG COUNTER
CLOCK RATES
BRG16 BRGH
BRG Counter Clock
0
0
1
1
Note:
0
FOSC/512
1
FOSC/128
0
FOSC/128
1
FOSC/32
During the ABD sequence, SPBRGx and
SPBRGHx are both used as a 16-bit
counter, independent of the BRG16 setting.
21.1.3.1 ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREGx cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 353