PIC18F47J53 Datasheet, PDF (441/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
28.0 SPECIAL FEATURES OF THE
CPU
PIC18F47J53 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
• Two-Speed Start-up
• Code Protection
• In-Circuit Serial Programming (ICSP)
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet. In
addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F47J53 family of
devices has a configurable Watchdog Timer (WDT),
which is controlled in software.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
28.1 Configuration Bits
The Configuration bits can be programmed to select
various device configurations. The configuration data is
stored in the last four words of Flash program memory;
Figure 6-1 depicts this. The configuration data gets
loaded into the volatile Configuration registers,
CONFIG1L through CONFIG4H, which are readable
and mapped to program memory, starting at location
300000h.
Table 28-2 provides a complete list. A detailed explana-
tion of the various bit functions is provided in
Register 28-1 through Register 28-6.
28.1.1
CONSIDERATIONS FOR
CONFIGURING THE PIC18F47J53
FAMILY DEVICES
Unlike some previous PIC18 microcontrollers, devices
of the PIC18F47J53 family do not use persistent mem-
ory registers to store configuration information. The
Configuration registers, CONFIG1L through
CONFIG4H, are implemented as volatile memory.
Immediately after power-up, or after a device Reset,
the microcontroller hardware automatically loads the
CONFIG1L through CONFIG4L registers with configu-
ration data stored in nonvolatile Flash program
memory. The last four words of Flash program memory,
known as the Flash Configuration Words (FCW), are
used to store the configuration data.
Table 28-1 provides the Flash program memory, which
will be loaded into the corresponding Configuration
register.
When creating applications for these devices, users
should always specifically allocate the location of the
FCW for configuration data. This is to make certain that
program code is not stored in this address when the
code is compiled.
The four Most Significant bits (MSb) of the FCW, corre-
sponding to CONFIG1H, CONFIG2H, CONFIG3H and
CONFIG4H, should always be programmed to ‘1111’.
This makes these FCWs appear to be NOP instructions
in the remote event that their locations are ever
executed by accident.
The four MSbs of the CONFIG1H, CONFIG2H,
CONFIG3H and CONFIG4H registers are not imple-
mented, so writing ‘1’s to their corresponding FCW has
no effect on device operation.
To prevent inadvertent configuration changes during
code execution, the Configuration registers,
CONFIG1L through CONFIG4L, are loaded only once
per power-up or Reset cycle. User’s firmware can still
change the configuration by using self-reprogramming
to modify the contents of the FCW.
Modifying the FCW will not change the active contents
being used in the CONFIG1L through CONFIG4H
registers until after the device is reset.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 441