PIC18F47J53 Datasheet, PDF (331/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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20.5.6.1 I²C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I²C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDAx while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted, 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. S and P conditions
are output to indicate the beginning and end of a serial
transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. S and P conditions indicate the beginning
and end of transmission.
The BRG used for the SPI mode operation is used to
set the SCLx clock frequency for either 100 kHz,
400 kHz or 1 MHz I²C operation. See Section 20.5.7
“Baud Rate” for more details.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
2. SSPxIF is set. The MSSP module will wait for
the required start time before any other
operation takes place.
3. The user loads the SSPxBUF with the slave
address to transmit.
4. The address is shifted out of the SDAx pin until
all 8 bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
7. The user loads the SSPxBUF with 8 bits of data.
8. Data is shifted out of the SDAx pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPxCON2<2>).
12. The interrupt is generated once the Stop
condition is complete.
20.5.7 BAUD RATE
In I²C Master mode, the BRG reload value is placed in
the lower seven bits of the SSPxADD register
(Figure 20-19). When a write occurs to SSPxBUF, the
Baud Rate Generator will automatically begin counting.
The BRG counts down to 0 and stops until another reload
has taken place. The BRG count is decremented twice
per instruction cycle (TCY) on the Q2 and Q4 clocks. In
I²C Master mode, the BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 20-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 331