PIC18F47J53 Datasheet, PDF (535/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 31-10: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
DC
Oscillator Frequency⁽¹⁾
4
1
TOSC
External CLKI Period⁽¹⁾
4
20.8
20.8
Oscillator Period⁽¹⁾
62.5
62.5⁽⁴⁾
2
TCY
Instruction Cycle Time⁽¹⁾
83.3
48
48
16
16⁽⁴⁾
—
—
250
250
DC
MHz
MHz
ns
ns
ns
EC Oscillator mode
ECPLL Oscillator mode⁽²⁾
HS Oscillator mode
HSPLL Oscillator mode⁽³⁾
EC Oscillator mode
ECPLL Oscillator mode⁽²⁾
HS Oscillator mode
HSPLL Oscillator mode⁽³⁾
TCY = 4/FOSC, Industrial
3
TOSL, External Clock in (OSC1)
10
TOSH
High or Low Time
—
ns EC Oscillator mode
4
TOSR, External Clock in (OSC1)
—
TOSF
Rise or Fall Time
7.5
ns EC Oscillator mode
Note 1:
2:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz.
3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12 or 16 MHz.
4: This is the maximum crystal/resonator driver frequency. The internal FOSC frequency when running from
the PLL can be up to 48 MHz.
TABLE 31-11: PLL CLOCK TIMING SPECIFICATIONS (VDDCORE = 2.35V TO 2.75V)
Param
No.
Sym
Characteristic
Min
Typ†
Max Units Conditions
F10 FOSC Oscillator Frequency Range
F11
FSYS On-Chip VCO System Frequency
F12
t_rc
PLL Start-up Time (lock time)
4
—
48 MHz
—
96
— MHz
—
—
2
ms
TABLE 31-12: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
No.
Device
Min Typ Max Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz⁽¹⁾
All Devices
-1 +0.15 +1
%
0°C to +85°C
VDD = 2.4V-3.6V
VDDCORE = 2.3V-2.7V
-1 +0.25 +1
%
INTRC Accuracy @ Freq = 31 kHz⁽¹⁾
-40°C to +85°C
VDD = 2.0V-3.6V
VDDCORE = 2.0V-2.7V
All Devices
20.3 — 42.2 kHz
-40°C to +85°C
VDD = 2.0V-3.6V
VDDCORE = 2.0V-2.7V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 535