PIC18F47J53 Datasheet, PDF (356/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
FIGURE 21-4:
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
1 TCY
bit 1
Word 1
Word 1
Transmit Shift Reg
bit 7/8 _{Stop bit}
FIGURE 21-5:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
1 TCY
Start bit
bit 0
Word 1
Transmit Shift Reg.
1 TCY
bit 1
Word 1
bit 7/8 _{Stop bit}
Start bit
bit 0
Word 2
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 21-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽¹⁾
PMPIE⁽¹⁾
PMPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
PIR3
SSP2IF BCL2IF RC2IF
TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3
SSP2IE BCL2IE RC2IE
TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3
SSP2IP BCL2IP RC2IP
TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
TXREGx
EUSARTx Transmit Register
TXSTAx
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE
ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx
EUSARTx Baud Rate Generator Register Low Byte
ODCON2
—
—
—
—
CCP10OD CCP9OD U2OD
U1OD
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These bits are only available on 44-pin devices.
DS39964B-page 356
Preliminary
 2010 Microchip Technology Inc.