PIC18F47J53 Datasheet, PDF (227/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
15.5.2 TIMER3/5 GATE SOURCE
SELECTION
The Timer3/5 gate source can be selected from one of
four different sources. Source selection is controlled by
the TxGSS<1:0> bits (TxGCON<1:0>). The polarity for
each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON<6>).
TABLE 15-2: TIMER3/5 GATE SOURCES
TxGSS<1:0>
Timerx Gate Source
00
TxG timer gate pin
01
TMR4/6 matches PR4/6
10
Comparator 1 output
11
Comparator 2 output
15.5.2.1 TxG Pin Gate Operation
The TxG pin is one source for Timer3/5 gate control. It
can be used to supply an external source to the gate
circuitry.
15.5.2.2 Timer4/6 Match Gate Operation
The TMR4/6 register will increment until it matches the
value in the PR4/6 register. On the very next increment
cycle, TMR4/6 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer3/5 gate
circuitry.
15.5.3 TIMER3/5 GATE-TOGGLE MODE
When Timer3/5 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer3/5
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 15-3.)
The TxGVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer3/5 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
FIGURE 15-3:
TIMER3/5 GATE TOGGLE MODE
TMRxGE
TxGPOL
TxGTM
TxG_IN
TxCKI
TxGVAL
Timer3/5
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7 N+8
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 227