PIC18F47J53 Datasheet, PDF (154/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 10-7: PORTC I/O SUMMARY⁽¹⁾ (CONTINUED)
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RC6/CCP9/
PMA5/TX1/
CK1/RP17
RC6
CCP9
1
I
ST PORTC<6> data input.
0
O DIG LATC<6> data output.
1
I
ST Capture input.
0
PMA5⁽²⁾
1
O DIG Compare/PWM output.
I ST/TTL Parallel Master Port io_addr_in<5>.
0
O DIG Parallel Master Port address.
TX1
0
O DIG Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as an output.
CK1
1
I
ST Synchronous serial clock input (EUSART module).
0
O DIG Synchronous serial clock output (EUSART module); takes
priority over port data.
RP17
1
I
ST Remappable Peripheral Pin 17 input.
0
O DIG Remappable Peripheral Pin 17 output.
RC7/CCP10/
RC7
1
I
ST PORTC<7> data input.
PMA4/RX1/
DT1/SDO1/
RP18
0
CCP10
1
O DIG LATC<7> data output.
I
ST Capture input.
0
O DIG Compare/PWM output.
PMA4⁽²⁾
x
I/O ST/TTL/ Parallel Master Port address.
DIG
RX1
1
I
ST Asynchronous serial receive data input (EUSART module).
DT1
1
1
ST Synchronous serial data input (EUSART module). User
must configure as an input.
0
O DIG Synchronous serial data output (EUSART module); takes
priority over port data.
SDO1
0
O DIG SPI data output (MSSP1 module).
RP18
1
I
ST Remappable Peripheral Pin 18 input.
0
O DIG Remappable Peripheral Pin 18 output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I²C/SMB = I²C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ53 devices.
2: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).
TABLE 10-8:
Name
PORTC
LATC
TRISC
ANCON1
CM2CON
UCON
UCFG
RTCCFG
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7
LATC7
TRISC7
VBGEN
CON
—
UTEYE
RTCEN
RC6
RC5
RC4
—
LATC6
—
—
—
TRISC6
—
—
—
—
—
PCFG12 PCFG11
COE
CPOL EVPOL1 EVPOL0
PPBRST
SE0
PKTDIS USBEN
UOEMON
—
UPUEN UTRDIS
—
RTCWREN RTCSYNC HALFSEC
RC2
LATC2
TRISC2
PCFG10
CREF
RESUME
FSEN
RTCOE
RC1
LATC1
TRISC1
PCFG9
CCH1
SUSPND
PPB1
RTCPTR1
RC0
LATC0
TRISC0
PCFG8
CCH0
—
PPB0
RTCPTR0
DS39964B-page 154
Preliminary
 2010 Microchip Technology Inc.