PIC18F47J53 Datasheet, PDF (233/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
16.0 TIMER4/6/8 MODULE
The Timer4/6/8 timer modules have the following
features:
• Eight-bit Timer register (TMRx)
• Eight-bit Period register (PRx)
• Readable and writable (all registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMRx match of PRx
Note: Throughout this section, generic references
are used for register and bit names that are the
same – except for an ‘x’ variable that indicates
the item’s association with the Timer4, Timer6
or Timer8 module. For example, the control
register is named TxCON and refers to
T4CON, T6CON and T8CON.
The Timer4/6/8 modules have a control register shown
in Register 16-1. Timer4/6/8 can be shut off by clearing
control bit, TMRxON (TxCON<2>), to minimize power
consumption. The prescaler and postscaler selection of
Timer4/6/8 are also controlled by this register.
Figure 16-1 is a simplified block diagram of the
Timer4/6/8 modules.
16.1 Timer4/6/8 Operation
Timer4/6/8 can be used as the PWM time base for the
PWM mode of the ECCP modules. The TMRx registers
are readable and writable, and are cleared on any
device Reset. The input clock (FOSC/4) has a prescale
option of 1:1, 1:4 or 1:16, selected by control bits,
TxCKPS<1:0> (TxCON<1:0>). The match output of
TMRx goes through a four-bit postscaler (that gives a
1:1 to 1:16 inclusive scaling) to generate a TMRx
interrupt, latched in the flag bit, TMRxIF. Table 16-1
gives each module’s flag bit.
TABLE 16-1: TIMER4/6/8 FLAG BITS
Timer Module
Flag Bit
4
PIR3<3>
6
PIR5<3>
8
PIR5<4>
The interrupt can be enabled or disabled by setting or
clearing the Timerx Interrupt Enable bit (TMRxIE),
shown in Table 16-2.
TABLE 16-2: TIMER4/6/8 INTERRUPT
ENABLE BITS
Timer Module
Flag Bit
4
PIE3<3>
6
PIE5<3>
8
PIE5<4>
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMRx register
• A write to the TxCON register
• Any device Reset (Power-on Reset (POR), MCLR
Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR))
A TMRx is not cleared when a TxCON is written.
Note:
The CCP and ECCP modules use Timers
1 through 8 for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 19-2,
Register 18-2 and Register 18-3.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 233