PIC18F47J53 Datasheet, PDF (274/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
19.3 Compare Mode
In Compare mode, the 16-bit CCPRx register pair value
is constantly compared against either the TMR1 or
TMR3 register pair value. When a match occurs, the
ECCPx pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
19.3.1 ECCP PIN CONFIGURATION
Users must configure the ECCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCPxCON register will force
the ECCPx compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTx I/O data
latch.
19.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
19.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the ECCPx pin is not affected;
only the CCPxIF interrupt flag is affected.
19.3.4 SPECIAL EVENT TRIGGER
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPRx registers to
serve as a Programmable Period register for either
timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
FIGURE 19-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
0
TMR1H TMR1L
1
TMR3H TMR3L
C1TSEL0
C1TSEL1
C1TSEL2
Comparator
Compare
Match
CCPR1H CCPR1L
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
Set CCP1IF
Output
Logic
SQ
R
4
CCP1CON<3:0>
ECCP1 Pin
TRIS
Output Enable
DS39964B-page 274
Preliminary
 2010 Microchip Technology Inc.