PIC18F47J53 Datasheet, PDF (541/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 31-18: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
PM1
PM2
PM3
PM5
PM6
PM7
PMALL/PMALH Pulse Width
—
Address Out Valid to PMALL/PMALH
—
Invalid (address setup time)
PMALL/PMALH Invalid to Address Out
—
Invalid (address hold time)
PMRD Pulse Width
—
PMRD or PMENB Active to Data In Valid
—
(data setup time)
PMRD or PMENB Inactive to Data In Invalid
—
(data hold time)
0.5 TCY
0.75 TCY
0.25 TCY
0.5 TCY
—
—
Max
Units
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
FIGURE 31-11: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
System
Clock
PMA<13:18>
Address
PMD<7:0>
PMRD
Address<7:0>
Data
PM12
PM13
PMWR
PMALL/
PMALH
PMCS<2:1>
PM11
PM16
Note: Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.
TABLE 31-19: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ
PM11
PM12
PM13
PM16
PMWR Pulse Width
Data Out Valid before PMWR or PMENB
goes Inactive (data setup time)
PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
PMCS Pulse Width
—
—
—
TCY – 5
0.5 TCY
—
—
—
Max
Units
—
ns
—
ns
—
ns
—
ns
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 541