PIC18F47J53 Datasheet, PDF (220/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 Match Interrupt Flag,
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscaler options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
T2OUTPS<3:0>
T2CKPS<1:0>
FOSC/4
4
2
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
Reset
TMR2
8
14.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the ECCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP modules operating in SPI mode.
Additional information is provided in Section 20.0
“Master Synchronous Serial Port (MSSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or MSSPx)
PR2
8
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽¹⁾
PMPIE⁽¹⁾
PMPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR2 Timer2 Register
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1
PR2
Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are only available in 44-pin devices.
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
T2CKPS0
DS39964B-page 220
Preliminary
 2010 Microchip Technology Inc.