PIC18F47J53 Datasheet, PDF (358/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
FIGURE 21-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREGx
Start
bit 7/8 Stop bit
bit
Word 2
RCREGx
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after
the third word causing the OERR (Overrun) bit to be set.
TABLE 21-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF⁽¹⁾
PMPIE⁽¹⁾
PMPIP⁽¹⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
PIR3
SSP2IF BCL2IF
RC2IF
TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RX9D
RCREGx
EUSARTx Receive Register
TXSTAx
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
BAUDCONx ABDOVF RCIDL
RXDTP TXCKP BRG16
—
WUE
ABDEN
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx
EUSARTx Baud Rate Generator Low Byte
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available on 44-pin devices.
21.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the
LIN/J2602 protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 21-8) and asynchronously if the device is in
Sleep mode (Figure 21-9). The interrupt condition is
cleared by reading the RCREGx register.
DS39964B-page 358
Preliminary
 2010 Microchip Technology Inc.