PIC18F47J53 Datasheet, PDF (289/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
19.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
will be set. The ECCPx will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
19.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced CCP modules
used on other PIC18 and PIC16 devices.
19.4.8.1 Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
TABLE 19-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8
File Name
INTCON
RCON
PIR1
PIR2
PIR4
PIE1
PIE2
PIE4
IPR1
IPR2
IPR4
TRISB
TRISC
TRISE
TMR1H
TMR1L
TMR2
TMR3H
TMR3L
TMR4
TMR6
TMR8
PR2
PR4
PR6
PR8
T1CON
T2CON
T3CON
T4CON
T6CON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
IPEN
—
CM
RI
TO
PMPIF
ADIF
RC1IF
TX1IF
SSP1IF
OSCFIF
CM2IF
CM1IF
USBIF
BCL1IF
CCP10IF
CCP9IF CCP8IF CCP7IF CCP6IF
PMPIE
ADIE
RC1IE
TX1IE
SSP1IE
OSCFIE
CM2IE
CM1IE
USBIE
BCL1IE
CCP10IE
CCP9IE CCP8IE CCP7IE CCP6IE
PMPIP
ADIP
RC1IP
TX1IP
SSP1IP
OSCFIP
CM2IP
CM1IP
USBIP
BCL1IP
CCP10IP
CCP9IP CCP8IP CCP7IP CCP6IP
TRISB7
TRISB6 TRISB5 TRISB4 TRISB3
TRISC7
TRISC6
—
—
—
RDPU
REPU
—
—
—
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer3 Register High Byte
Timer3 Register Low Byte
Timer4 Register
Timer6 Register
Timer8 Register
Timer2 Period Register
Timer4 Period Register
Timer6 Period Register
Timer8 Period Register
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
—
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0
Bit 2
TMR0IF
PD
CCP1IF
HLVDIF
CCP5IF
CCP1IE
HLVDIE
CCP5IE
CCP1IP
HLVDIP
CCP5IP
TRISB2
TRISC2
TRISE2
T1SYNC
TMR2ON
T3SYNC
TMR4ON
TMR6ON
Bit 1
INT0IF
POR
TMR2IF
TMR3IF
CCP4IF
TMR2IE
TMR3IE
CCP4IE
TMR2IP
TMR3IP
CCP4IP
TRISB1
TRISC1
TRISE1
RD16
T2CKPS1
RD16
T4CKPS1
T6CKPS1
Bit 0
RBIF
BOR
TMR1IF
CCP2IF
CCP3IF
TMR1IE
CCP2IE
CCP3IE
TMR1IP
CCP2IP
CCP3IP
TRISB0
TRISC0
TRISE0
TMR1ON
T2CKPS0
TMR3ON
T4CKPS0
T6CKPS0
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 289